Conventionally, IC packages utilized 0 and 5 volts voltage levels to represent “0” and “1” logic states respectively. However, with advancement in technology, these voltage levels have undergone a change. For example in many current IC devices manufactured by submicron semiconductor fabrication processes, a voltage level of 3.3 volts is used instead of 5 volts to represent logic state “1”. This reduction in the voltage level has lead to reduced power dissipation and hence improved performance of the IC devices. With the introduction of lower voltage levels, present day IC devices work in mixed mode operation. In such a mode, circuits operating at 3.3 volts and 5 volts are coupled together. This coupling of different circuits, however, may lead to interfacing problems. If the voltage applied to the low voltage circuitry gets too high, some devices may experience temporary or even permanent damage. The Metal Oxide Semiconductor (MOS) transistors can be subjected to dielectric damage and reliability problems due to the excessive voltage developed across the gate oxide.
In addition to this, there are many applications in which the integrated circuit is required to operate across wide power supply range (e.g. 1.5 to 3.6 volts) and also require high noise immunity due to extreme environmental conditions. Generally, 3.3 volt devices are used in such circuits, which need to operate across the full power supply range. To guarantee the full functionality of the circuit across this large supply and temperature range, without exposing the gate oxide of transistors to a voltage stress together with maintaining a high noise margin is unachievable by using the conventional circuits.
High voltage tolerant input buffers are used in present day integrated circuits in order to overcome the above-mentioned interfacing problems. A conventional high voltage tolerant input buffer has been shown in the form of block diagram in FIG. 1. The buffer receives the input signal from external circuits at the input node PAD, and transmits the signal to core through node ZI. The basic structure of the high volt tolerant input buffer comprises of an NMOS pass transistor (101), an inverting input stage (102), a CMOS inverter (103) and a PMOS transistor (104). The function of NMOS pass transistor (101) is to protect the inverting input stage (102) from the voltage at the node PAD which can be higher than the power supply of the inverting input stage, VDD. The inverting input stage (102) may be a Schmitt Trigger circuit which adds hysteresis or a typical CMOS inverter stage. The CMOS inverter (103) transmits the signal to core with sufficient drive capability, after receiving it from inverting input stage (102). The PMOS transistor (104) is also known as “keeper” device. Whenever a high voltage signal arrives at input node PAD, the NMOS pass transistor (101) limits the voltage at node A to approximately a threshold voltage below the supply voltage VDD (i.e., VDD−Vthn) where Vthn denotes the threshold voltage of an NMOS transistor (101). The voltage (VDD−Vthn) at node A switches the state of inverting input stage (102) Schmitt Trigger, bringing the voltage at node B from VDD to 0 volts. The PMOS keeper transistor (104) has its gate terminal connected to node B, Source terminal to supply VDD and the Drain terminal to node A. When voltage at node B drops from VDD to 0, the PMOS keeper transistor (104) turns ON and pulls the voltage of node A from VDD−Vthn to VDD. The PMOS keeper transistor thus, turns off completely the PMOS of the inverting input stage (102). This prevents flow of leakage current through inverting input stage (102) from VDD to ground.
The conventional circuit as explained above, however, fails to function when the circuit works at large supply range (for example 1.5 volts to 3.6 volts). In such circuits, 3.3 volt transistors are made to operate at very low supply voltages (example 1.5 volts). The conventional circuits do not guarantee full functionality across this large supply and temperature range, without exposing the gate oxide of transistors to a voltage stress together with maintaining a high noise margin. In the circuit explained, the inverting input stage Schmitt Trigger (102) switches its state only when the voltage at node A crosses the high level threshold (VIH) of the inverting input stage Schmitt Trigger (102). At low temperatures, the threshold voltage Vthn of the NMOS pass gate (101) is very high. This causes the voltage at node A (VDD−Vthn) to be limited to a very low value. If the voltage at node A is not high enough to cross the threshold (VIH) of inverting input stage (102), then the voltage at node B remains approximately VDD regardless of the voltage at node PAD. As a result, the PMOS keeper (104) does not turn on. This makes the circuit non-functional and also results in a very high leakage current flowing through the input stage from VDD to ground. This problem can be avoided by using a low-threshold transistor as NMOS pass transistor (101). However, that requires some extra masks during fabrication process, which in turn increases the cost of manufacturing.
Therefore, there arises a need for an input buffer, which tolerates high voltage and at the same time can operate across wide range of power supply.
There is yet another need for a high voltage tolerant input buffer which maintains fast speed of operation even at low power supply voltages without any increase in cost or process complexity.